When we develope a project , there may so many files and may be larger files i mean programs.(1) So recompiling large programs takes more time then shorter one.
(2)Suppose i have made chage to one file, so i do't need to recompile other files.
(3) The make program helps us in developing our large programs by keeping track of which portions of the entire program have been changed, compiling only those parts of the program which have changed since the last compile.
all these can be achived by a utility called Make. So we can have set of guide lines i.e rules to be followed for this utility.
Before that i just want some brush up some basics of compiling.
Basically there is 3 steps fo building the program.
step 1
Compiler stage: All C/C++ language code in the .c/cpp file is converted into a lower-level language called Assembly language; making .s files.
step 2
Assembler stage: The assembly language code made by the previous stage is then converted into object code which are fragments of code which the computer understands directly. An object code file ends with .o.
step 3
Linker stage: The final stage in compiling a program involves linking the object code to code libraries which contain certain "built-in" functions, such as printf. This stage produces an executable program, which is named a.out by default
Note : Definition i have taken from net.
Source file assembler linker executable
.................. ..................
.c and .h ------> .s-----> file .o ---> do liniking ----> then finaly we get executable
Sample make file.
Project1: data.o main.o io.o
cc data.o main.o io.o –o project1
Data.o: data.c data.h
cc –c data.c
Main.o: data.h io.h main.c
cc –c main.c
Io.o: io.h io.c
cc –c io.c
we need " makefile " to tell “ make “ what to do.The makefile tells `make' how to compile and link a program.
When `make' recompiles each changed source file must be recompiled.
What are the files afected,if some thing changed ..?
If header changed then
Each C/C++ source file that includes the header file must be recompiled which will produce the
object file corresponding to the source file.
What make does after recompiling the changed files.?
All the object files, whether newly created or saved from previous compilations, are to be linked together to produce the new executable . so we can say linking is done after compilation and then the executable.
Here some of the option i am listing out which is generally used with compiler , i am using gcc.
gcc –c option is used to generate object file( .o file).
gcc –g option is used to debug the executable file
gcc –o is used to give different name for executable instead of a.out.
gcc –DDEBUG=3 is used to Define the macro whose name is DEBUG whose value is 3.
-I option is used to include the path of Header files.
-L option is used to include the path of Library files.
-l( small L) option is used to include the library(.a or .so ).
In Make file , what is -lc, or -lm i don't understand ?
If the library name is libc.a or libc.so , we can include this library using –l option like this –lc where lib and .a/.so by default not required. so we write like this,do,t get confused.
Is there any rules like dependency or target?
Yes
Make files contain dependency rules and construction rules.
What is dependency rule?
It has two parts - a left and right side separated by a :
left side : right side
The left side gives the names of a target(s) (the names of the program or system files) to be built, whilst the right side gives names of files on which the target depends (eg. source files, header files, data files)
Another example.
program1 : main.o test.o command.o
cc -o program1 main.o test.o command.o
main.o : main.c defs.h
cc -c main.c
test.o : test.c defs.h command.h
cc -c kbd.c
command.o : command.c defs.h command.h
cc -c command.c
Here program1 is executable name.
we will use –c is generate .o file.
cc –c main.c will generate main.o
main.o : main.c defs.h => means main.o depends on main.c and defs.h header file.
here will use cc –o program1 to specify executable name as “program1” otherwise by default it will be a.out
we can use macros in make files.
Make macros :-
SOURCES= main.c f1.c f2.c ( ALL C FILES )
CFLAGS=-g –c ( -g for debugging and –c created .o files )
LFLAGS=-L/usr/lib ( Library PATHNAME )
LIBS=-lm /usr/local/calculation.a ( Library )
There are lots of short cut symbols are ther we can use that
here is the examples.
1) "$< " is shorthand for file name with .c extension
Ex:-
show.o : show.c
cc –c $< Here "$< " show.c
2) $@ is full target name of current target.
Ex:-
edit : show.o
cc –o $@ show.o
Here $@ is edit
example of make file using macros
OBJECTS=main.o f1.o f2.o
LFLAGS=-L/usr/lib -L/home/sahu/cprog
LIBS=/home/sahu/cprog/show.a –lc #Here –lc means libc.a lib and .a are default
CFLAGS=-g -c
INCLUDES=-I/usr/include -I/home/sahu
main.exe : $(OBJECTS)
cc -o main.exe $(LFLAGS) $(OBJECTS) $(LIBS)main.o:main.c
cc $(CFLAGS) $(INCLUDES) main.c
f1.o:f1.c
cc $(CFLAGS) $(INCLUDES) f1.c
f2.o:f2.c
cc $(CFLAGS) $(INCLUDES) $< #Here $<>
clean:
rm -f $(OBJECTS) main.exe
BACKSLASH:-
A backslash( \ ) at the end of the line means that the command is continued on the next line.
Example:-
edit : main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o
MAKEFILE USING IMPLICIT RULES:-
Example:-
OBJECTS=main.o h.o v.o
LFLAGS=-L/usr/lib -L/home/sahu/cprog
LIBS=/home/sahu/cprog/show.a -lc
CFLAGS=-g -c
INCLUDES=-I/usr/include -I/home/sahu
main.exe: $(OBJECTS)
cc -o main.exe $(LFLAGS) $(OBJECTS) $(LIBS)
.c.o:
cc -c $(INCLUDES) $(CFLAGS) $< color="#ff0000">Below Line is called Implicit Rule.
.c.o:
cc -c $(INCLUDES) $(CFLAGS) $<
Meaning of line .c.o: is using .c file we will get .o file.$<>
Now we understand some thing by which we can write a simple Make file.We can name it Makefile or makefile then at the command prompt we can write simply make , if we want to run other then these two name then we have to write make -f makefile name
Next article i will try to write some other macros and little bit bigger make files.
Cheer,
Sahu
hara.sahu@gmail.com
Thursday, August 23, 2007
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